Sat, 18 Sep 2021 16:03:12 UTC

Information for RPM iverilog-0.9.20110317-1.fc16.x86_64.rpm

ID2559985
Nameiverilog
Version0.9.20110317
Release1.fc16
Epoch
Archx86_64
SummaryIcarus Verilog is a verilog compiler and simulator
DescriptionIcarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
Build Time2011-05-27 23:01:48 GMT
Size1,209,024
cb1579b2e2a6bba88658bbbe334f0954
LicenseGPLv2
Buildrootf16-build-1070763-161967
Provides
cadpli.vpl()(64bit)
iverilog = 0.9.20110317-1.fc16
iverilog(x86-64) = 0.9.20110317-1.fc16
iverilog-devel = 0.9.20110317-1.fc16
null.tgt()(64bit)
stub.tgt()(64bit)
system.vpi()(64bit)
v2005_math.vpi()(64bit)
va_math.vpi()(64bit)
vhdl.tgt()(64bit)
vvp.tgt()(64bit)
Obsoletes
iverilog-devel < 0.9.20100911-1
Conflicts No Conflicts
Requires
libbz2.so.1()(64bit)
libc.so.6()(64bit)
libc.so.6(GLIBC_2.14)(64bit)
libc.so.6(GLIBC_2.2.5)(64bit)
libc.so.6(GLIBC_2.3)(64bit)
libc.so.6(GLIBC_2.3.4)(64bit)
libc.so.6(GLIBC_2.4)(64bit)
libc.so.6(GLIBC_2.7)(64bit)
libdl.so.2()(64bit)
libdl.so.2(GLIBC_2.2.5)(64bit)
libgcc_s.so.1()(64bit)
libgcc_s.so.1(GCC_3.0)(64bit)
libgcc_s.so.1(GCC_4.0.0)(64bit)
libm.so.6()(64bit)
libm.so.6(GLIBC_2.2.5)(64bit)
libstdc++.so.6()(64bit)
libstdc++.so.6(CXXABI_1.3)(64bit)
libstdc++.so.6(GLIBCXX_3.4)(64bit)
libstdc++.so.6(GLIBCXX_3.4.11)(64bit)
libstdc++.so.6(GLIBCXX_3.4.15)(64bit)
libstdc++.so.6(GLIBCXX_3.4.9)(64bit)
libz.so.1()(64bit)
rpmlib(CompressedFileNames) <= 3.0.4-1
rpmlib(FileDigests) <= 4.6.0-1
rpmlib(PayloadFilesHavePrefix) <= 4.0-1
rpmlib(PayloadIsXz) <= 5.2-1
rtld(GNU_HASH)
Recommends No Recommends
Suggests No Suggests
Supplements No Supplements
Enhances No Enhances
Files
Page:
1 through 50 of 67 >>>
Name ascending sort Size
/usr/bin/iverilog40,928
/usr/bin/iverilog-vpi3,070
/usr/bin/vvp708,904
/usr/include/_pli_types.h2,478
/usr/include/acc_user.h7,583
/usr/include/ivl_target.h82,177
/usr/include/veriuser.h11,557
/usr/include/vpi_user.h18,764
/usr/lib64/ivl4,096
/usr/lib64/ivl/cadpli.vpl44,056
/usr/lib64/ivl/include4,096
/usr/lib64/ivl/include/constants.vams1,377
/usr/lib64/ivl/include/disciplines.vams1,125
/usr/lib64/ivl/ivl1,607,912
/usr/lib64/ivl/ivlpp48,688
/usr/lib64/ivl/null-s.conf65
/usr/lib64/ivl/null.conf18
/usr/lib64/ivl/null.tgt4,872
/usr/lib64/ivl/stub-s.conf96
/usr/lib64/ivl/stub.conf49
/usr/lib64/ivl/stub.tgt57,408
/usr/lib64/ivl/system.sft620
/usr/lib64/ivl/system.vpi272,736
/usr/lib64/ivl/v2005_math.sft632
/usr/lib64/ivl/v2005_math.vpi12,456
/usr/lib64/ivl/va_math.sft215
/usr/lib64/ivl/va_math.vpi8,824
/usr/lib64/ivl/vhdl-s.conf103
/usr/lib64/ivl/vhdl.conf49
/usr/lib64/ivl/vhdl.tgt280,208
/usr/lib64/ivl/vvp-s.conf128
/usr/lib64/ivl/vvp.conf81
/usr/lib64/ivl/vvp.tgt140,992
/usr/lib64/libveriuser.a68,928
/usr/lib64/libvpi.a1,378
/usr/share/doc/iverilog-0.9.201103174,096
/usr/share/doc/iverilog-0.9.20110317/BUGS.txt7,554
/usr/share/doc/iverilog-0.9.20110317/COPYING17,990
/usr/share/doc/iverilog-0.9.20110317/README.txt17,703
/usr/share/doc/iverilog-0.9.20110317/attributes.txt2,911
/usr/share/doc/iverilog-0.9.20110317/cadpli.txt1,665
/usr/share/doc/iverilog-0.9.20110317/examples4,096
/usr/share/doc/iverilog-0.9.20110317/examples/clbff.v3,371
/usr/share/doc/iverilog-0.9.20110317/examples/des.v47,932
/usr/share/doc/iverilog-0.9.20110317/examples/hello.vl1,632
/usr/share/doc/iverilog-0.9.20110317/examples/hello_vpi.c2,361
/usr/share/doc/iverilog-0.9.20110317/examples/hello_vpi.vl1,667
/usr/share/doc/iverilog-0.9.20110317/examples/outff.v2,826
/usr/share/doc/iverilog-0.9.20110317/examples/pal_reg.v4,366
/usr/share/doc/iverilog-0.9.20110317/examples/show_vcd.vl3,911
Component of
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Buildroot descending sort Created State
f16-build-1111928-171802 2011-07-31 13:42:43 expired
f17-build-1111862-171816 2011-07-31 11:15:45 expired
f16-build-1111849-171802 2011-07-31 10:49:47 expired
f16-build-1111843-171802 2011-07-31 10:22:17 expired
f16-build-1111839-171802 2011-07-31 10:11:01 expired