Mon, 20 Sep 2021 08:34:01 UTC

Information for RPM iverilog-0.9.20111101-1.fc17.i686.rpm

ID2773407
Nameiverilog
Version0.9.20111101
Release1.fc17
Epoch
Archi686
SummaryIcarus Verilog is a verilog compiler and simulator
DescriptionIcarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
Build Time2011-11-01 20:14:13 GMT
Size1,219,777
400efeb103b750ec6e6d2c04a566a22a
LicenseGPLv2
Buildrootf17-build-1172381-185009
Provides
cadpli.vpl
iverilog = 0.9.20111101-1.fc17
iverilog(x86-32) = 0.9.20111101-1.fc17
iverilog-devel = 0.9.20111101-1.fc17
null.tgt
stub.tgt
system.vpi
v2005_math.vpi
va_math.vpi
vhdl.tgt
vvp.tgt
Obsoletes
iverilog-devel < 0.9.20100911-1
Conflicts No Conflicts
Requires
/bin/sh
libbz2.so.1
libc.so.6
libc.so.6(GLIBC_2.0)
libc.so.6(GLIBC_2.1)
libc.so.6(GLIBC_2.1.3)
libc.so.6(GLIBC_2.2)
libc.so.6(GLIBC_2.3)
libc.so.6(GLIBC_2.3.4)
libc.so.6(GLIBC_2.4)
libc.so.6(GLIBC_2.7)
libdl.so.2
libdl.so.2(GLIBC_2.0)
libdl.so.2(GLIBC_2.1)
libgcc_s.so.1
libgcc_s.so.1(GCC_3.0)
libgcc_s.so.1(GCC_4.0.0)
libgcc_s.so.1(GLIBC_2.0)
libm.so.6
libm.so.6(GLIBC_2.0)
libm.so.6(GLIBC_2.1)
libstdc++.so.6
libstdc++.so.6(CXXABI_1.3)
libstdc++.so.6(GLIBCXX_3.4)
libstdc++.so.6(GLIBCXX_3.4.11)
libstdc++.so.6(GLIBCXX_3.4.15)
libstdc++.so.6(GLIBCXX_3.4.9)
libz.so.1
rpmlib(CompressedFileNames) <= 3.0.4-1
rpmlib(FileDigests) <= 4.6.0-1
rpmlib(PayloadFilesHavePrefix) <= 4.0-1
rpmlib(PayloadIsXz) <= 5.2-1
rtld(GNU_HASH)
Recommends No Recommends
Suggests No Suggests
Supplements No Supplements
Enhances No Enhances
Files
Page:
1 through 50 of 67 >>>
Name ascending sort Size
/usr/bin/iverilog38,500
/usr/bin/iverilog-vpi3,105
/usr/bin/vvp694,476
/usr/include/_pli_types.h2,478
/usr/include/acc_user.h7,583
/usr/include/ivl_target.h82,593
/usr/include/veriuser.h11,557
/usr/include/vpi_user.h18,764
/usr/lib/ivl4,096
/usr/lib/ivl/cadpli.vpl42,860
/usr/lib/ivl/include4,096
/usr/lib/ivl/include/constants.vams1,377
/usr/lib/ivl/include/disciplines.vams1,125
/usr/lib/ivl/ivl1,607,832
/usr/lib/ivl/ivlpp46,592
/usr/lib/ivl/null-s.conf65
/usr/lib/ivl/null.conf18
/usr/lib/ivl/null.tgt3,788
/usr/lib/ivl/stub-s.conf96
/usr/lib/ivl/stub.conf49
/usr/lib/ivl/stub.tgt53,772
/usr/lib/ivl/system.sft653
/usr/lib/ivl/system.vpi305,592
/usr/lib/ivl/v2005_math.sft632
/usr/lib/ivl/v2005_math.vpi13,984
/usr/lib/ivl/va_math.sft215
/usr/lib/ivl/va_math.vpi9,672
/usr/lib/ivl/vhdl-s.conf103
/usr/lib/ivl/vhdl.conf49
/usr/lib/ivl/vhdl.tgt265,644
/usr/lib/ivl/vvp-s.conf128
/usr/lib/ivl/vvp.conf81
/usr/lib/ivl/vvp.tgt150,140
/usr/lib/libveriuser.a57,446
/usr/lib/libvpi.a1,014
/usr/share/doc/iverilog-0.9.201111014,096
/usr/share/doc/iverilog-0.9.20111101/BUGS.txt7,554
/usr/share/doc/iverilog-0.9.20111101/COPYING17,990
/usr/share/doc/iverilog-0.9.20111101/README.txt17,703
/usr/share/doc/iverilog-0.9.20111101/attributes.txt2,911
/usr/share/doc/iverilog-0.9.20111101/cadpli.txt1,665
/usr/share/doc/iverilog-0.9.20111101/examples4,096
/usr/share/doc/iverilog-0.9.20111101/examples/clbff.v3,371
/usr/share/doc/iverilog-0.9.20111101/examples/des.v47,932
/usr/share/doc/iverilog-0.9.20111101/examples/hello.vl1,632
/usr/share/doc/iverilog-0.9.20111101/examples/hello_vpi.c2,361
/usr/share/doc/iverilog-0.9.20111101/examples/hello_vpi.vl1,667
/usr/share/doc/iverilog-0.9.20111101/examples/outff.v2,826
/usr/share/doc/iverilog-0.9.20111101/examples/pal_reg.v4,366
/usr/share/doc/iverilog-0.9.20111101/examples/show_vcd.vl3,911
Component of
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Buildroot descending sort Created State
f17-build-1239649-196217 2012-01-15 03:06:24 expired
f17-build-1238414-196211 2012-01-15 01:16:46 expired
f17-build-1220058-195884 2012-01-13 03:12:04 expired