Wed, 04 Aug 2021 19:29:53 UTC

Information for RPM verilator-3.845-1.fc19.src.rpm

ID3739983
Nameverilator
Version3.845
Release1.fc19
Epoch
Archsrc
SummaryA fast simulator for synthesizable Verilog
Description Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
Build Time2013-02-16 15:22:05 GMT
Size1,876,123
7717e1b995793c95c5817a6ed28b5337
LicenseGPLv2
Buildrootf19-build-1587087-271020
Provides No Provides
Obsoletes No Obsoletes
Conflicts No Conflicts
Requires
bison
flex
perl
perl-SystemPerl-devel
rpmlib(CompressedFileNames) <= 3.0.4-1
rpmlib(FileDigests) <= 4.6.0-1
Recommends No Recommends
Suggests No Suggests
Supplements No Supplements
Enhances No Enhances
Files
1 through 2 of 2
Name ascending sort Size
verilator-3.845.tgz1,873,811
verilator.spec4,662
Component of No Buildroots